1. Field of the Invention
The present invention relates to a semiconductor package, and more particularly, to a ball grid array (BGA) package with two or more stacked semiconductor chips and a method of manufacturing the same.
2. Description of the Related Art
A semiconductor chip packaging process may be a process of manufacturing semiconductor chips. Semiconductor chip packages may be used to electrically connect semiconductor chips to external apparatuses, protect the semiconductor chips from external enviroment by molding, and/or to dissipate heat. There are a variety of methods of electrically connecting semiconductor chips to external apparatuses; a BGA packaging process is an example. BGA packaging processes are used to manufacture high-speed, high-performance semiconductor packages by increasing the number of external connection terminals.
Recently, to increase the performance of electronic products including semiconductor chips, the semiconductor chips have been scaled down and/or become lighter. To achieve this, various semiconductor packaging methods have been developed. For example, flip chip package (FCP), chip scale package (CSP), or multi chip package (MCP) methods are widely used.
In the MCP method, two or more semiconductor chips of the same or different type are mounted on a single substrate. Semiconductor chips in an MCP may be arranged in series on the same level and/or be sequentially stacked in a vertical direction. The stacking of semiconductor chips may be better for small-sized electronic products since the area occupied by a package can be reduced to enable the CSP method.
FIG. 1 is a cross-sectional view of a conventional package with stacked semiconductor chips, which is disclosed in Korean Patent Laid-open Publication No. 2001-0056937.
Referring to FIG. 1, semiconductor chips 10 and 12, beneath which bonding pads 11 and 13 are respectively mounted, may be adhered to lead frames 20 and 50 having inner leads 21 and 51 and outer leads 22 and 52. A plurality of protrusions 23 and 53 may be formed in the center of the bottoms of the lead frames 20 and 50. Epoxy molding compounds (EMCs) 60 and 61 may cover the sides and the top surfaces of the semiconductor chips 10 and 12. The outer leads 22 and 52 may be exposed on both sides of the EMCs 60 and 61, and portions (for example, the bottom as shown in FIG. 1) of the protrusions 23 and 53 may also be exposed. An upper penetration hole 24 and a lower penetration hole 54, which are formed in the outer leads 22 and 52, respectively, may be electrically connected to each other by solder balls 70. Also, solder balls 71 for connecting external terminals are mounted on the protrusions 53 of the lower lead frame 50.
In a conventional package with stacked semiconductor chips, semiconductor chips may be stacked on lead frames that all have the same shape, and it may be possible to reinforce the adhesion between the stacked semiconductor chips. However, conventional packages with stacked semiconductor chips may have the following disadvantages.
First, because an EMC may cover the top surface of a semiconductor chip (as shown in FIG. 1), the height of a package with stacked semiconductor chips may be greater than the sum of the thicknesses of the lead frames (or substrates) and the semiconductor chips. This leads to an increase in the thickness of the overall semiconductor packages, which may hinder the manufacture of thinner semiconductor packages.
Second, solder balls for connecting packages may be exposed to an external environment. That is, because portions for connecting packages are not molded by an EMC, the reliability of the conventional package with stacked semiconductor chips may be degraded after using the package for many hours.
Korean Patent Laid-open Publication No. 2002-0043435 and Korean Patent Registration No. 0271656 propose examples of packages with stacked semiconductor chips and methods of manufacturing the same, which may have the same disadvantages as the package shown in FIG. 1. Further, a conductive post disclosed in Korean Patent Laid-open Publication No. 2002-0043435 may be inadequate for mass production considering the manufacturing cost and/or process complexity.